PMT control and status
| PD | Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high. |
| MPE | Magic packet enable When set, enables generation of a power management event due to Magic Packet reception. |
| WFE | Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception. |
| RESERVED | Reserved |
| MPR | Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register. |
| WFR | Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field. When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register. |
| RESERVED | Reserved |
| GU | Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame. |
| RESERVED | Reserved |
| WFFRPR | Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field. When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle. |